1. Field of the Invention
The present invention relates in general to the field of information handling system memory usage, and more particularly to a system and method for mapping virtual and physical memory pages to optimize memory use.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
Information handling systems typically perform desired tasks by running applications on top of an operating system, such as WINDOWS, that manages the use of physical components by the application, such as random access memory (RAM) or other memory resources. For instance, applications require some amount of virtual address space to store information during execution of the application. Memory mapping is typically in a CPU hardware map with the operating system setting up the mapping of virtual memory to physical memory and dynamically loading a portion of the mapping into the hardware map. The operating system typically allocates some amount of physical memory to be mapped from the application's virtual address space. The operating system performs this allocation to a granularity referred to as virtual memory pages. To varying extents, applications will exhibit spatial locality of reference within these virtual memory pages and specifically within consecutive virtual memory pages by using the virtual memory pages in sequential order. Physical memory system terminology also uses the term “page” to describe information storage. In physical system memory a page refers to the amount of data pulled from storage arrays on a single row address strobe (RAS) operation. This physical memory page may include multiple devices and multiple standard 64 bit interfaces, such as JDEC's PC2100 standard interfaces. Information in a physical memory page is available for repeated accesses with column address strobe (CAS) cycles. A physical memory page acts as a cache for future accesses and spatial locality of reference within physical memory pages is of value for more rapid information retrievals. Over time as applications or portions of applications are loaded and removed from physical memory, allocation of virtual pages to physical memory pages becomes random in that the probability that consecutive virtual pages map to a signal physical page is only related to the number of physical pages available.
In the past, information handling systems typically had virtual memory pages that were larger or equal to physical memory pages so that one or more physical memory pages are used to store a single virtual memory page. If virtual memory pages use one or more physical memory pages, the virtual memory page is effectively cached in the physical memory pages. However, storage capacity and speed of physical memory systems has steadily improved over the past several years with more dense devices that read greater amounts of information with each row address strobe. For instance, some dual channel interleaved memory systems have 128 bit wide access with one access strobe reading a double wide amount of stored information. As a result of the improvements to physical memory page size, physical memory pages are larger than virtual memory pages with increasing frequency in information handling systems having up-to-date physical memory systems. When physical memory pages are larger than a virtual memory page, the probability is significantly reduced that the available information in a physical memory page in excess of the size of a virtual memory page will act as an effective cache. In other words, a strobe of a physical memory page will recall the virtual memory page plus additional information stored in the physical memory page. In applications that rely on rapid memory accesses, such as streaming applications, inefficiencies are introduced with a physical memory page having multiple non-consecutive virtual memory pages since the probability that all of the information retrieved will be usable is very low.